CMC 2023 Conference Speaker Abstracts

Session 1: Global Issues & Trends Impacting Materials

“The Road to $1 Trillion Through Peaks and Valleys,” Risto Puhakka, Key Accounts, and Taylor St. Germain, Forecasting Analyst, at TechInsights

The semiconductor industry is in the middle of a downturn and is expected to finish 2023 in negative territory for the first time since 2019. TechInsights’ Forecasting Analyst, Taylor St. Germain, will review how key semiconductor verticals and suppliers will be impacted by the downturn. He will also explain the expected recovery that will characterize the semiconductor market in 2024 and 2025.

TechInsights’ Analyst will talk about trends in Sales, Shipments, and ASPs across the value chain. While there are several perspectives on the path to $1 trillion for the semiconductor industry, Taylor will share TechInsights’ interpretation of the timeline for this historic achievement.

“Globalization vs. Regionalization – Impact of Geopolitical Tensions and Lessons Learned,” Corinna Singer, Senior Dir. of Procurement at Infineon

This talk will focus on the trend of material supply chains in various regions of the world – why are some growing while others are shrinking? What can be done to counteract this trend or is it a lost cause? The impact of geopolitical tensions on the supply-chain will also be provided along with lessons learned to manage supply chains as demand heats up from chip expansions.

“Semiconductor Devices for Automotive Applications: What are the Market and Technologies Evolutions Expected?,” Jeff Perkins, EVP & GM at Yole

“Latest Advances in Silicon Wafers Targeted for RF Devices,” Jim Reed, VP, Key Account Development at Okmetic

Latest advances in 5G and 6G platforms are challenging the RF landscape. The increased band count with higher frequencies is setting new performance standards for RF filters and other related RF devices (IPD’s, Switches, Amplifiers, Antenna Tuners). These new product innovations require new baselines characteristics and performance metrics and drive new product development also at the substrate suppliers.

In the substrate market, there is a clear demand trend towards wafers with higher resistivity and value-added features such as trap-rich layers and enhanced surface geometries. Engineered Ultra High Resistivity wafers with trap-rich surface treatment have proven to improve RF filter and device performance significantly. These wafers enable RF filters and devices to reach very low H2 and IMD3 levels, low insertion losses and high Q values.

Session 2: Heterogenous Integration & Advanced Packaging Materials

“Substrate Opportunities and Challenges in the Heterogenous Integration,” Dilan Seneviratne, PhD, Dir. of Substrate Packaging Materials at Intel

Conventional thinking of Advanced Packaging centers around bump pitch and IO density scaling. However, with the aggressive demands driving the increased computational needs in data centers, more features need to be considered and developed. This talk will address key materials and process capabilities needed on high density interconnect substrates to meet the Advanced Packaging demands in the Heterogenous Integration era.

“Advanced Semiconductor Underfills,” Rose Guino, PhD, Principal Applications Engineer at Henkel

Semiconductor manufacturing processes and package configurations continue to increase in complexity to meet market demands. Advanced packaging and heterogeneous integration designs that enable the functionality of many applications, including 5G mobile telecom and data center high-performance computing, are challenged to achieve reliability metrics alongside operational expectations. However, the new architectures are essential for technology advancement, making material innovation a key element of next-generation device success. Large package body and die dimensions, a wide range of CTE considerations in a single package, and increasing chip and interconnect densities may result in warpage and stress-related conditions. Package-level underfill technology helps control for many of these factors, but understanding the range of formulations and their application benefits can be challenging.

In this talk, several underfill solutions for various levels of integration, including flip-chip, PoP, SiP, 2.5D, and 3D will be presented. Process, material characteristics, and reliability performance considerations for pre-applied non-conductive paste (NCP) and non-conductive film (NCF), as well as post-applied capillary underfill (CUF) and the new liquid compression molding – molded underfill (LCM-MUF) will be discussed.

“Thin Glass for Advanced Packaging Applications,” Shelby Nelson, Chief Technology Officer at Mosaic Microsystems

The properties of glass are driving interest in glass interposers for heterogeneous integration applications, chiplets, high performance computing, and sub-terahertz radio frequency communications. With its insensitivity to moisture, high dimensionally stability, and low surface roughness, glass has interposer properties that match silicon, and adds a high bulk resistivity that can provide very low loss at millimeter-wave frequencies. We describe a precision process for creating custom through-glass vias in thin glass, and a robust, manufacturable approach that allows glass to be handled with high yield in industry-standard equipment. We will discuss thin glass interposers including void-free precision through glass vias, redistribution layers, and integrated passive devices, as well as examples of millimeter-wave antenna arrays.

“Direct Atomic Layer Processing for Backend,” Jaim Nulman PhD, Chief Product Officer and President at Atlant 3D

This presentation will introduce the unique patent pending technology being commercialized by ATLANT 3D: Direct Atomic Layer Processing (DALPTM). This lithography-less processing technology provides digitally controlled deposition, etching, cleaning and other processing steps with a variety of materials. The technology is being applied to semiconductor devices, packaging, MEMS, optics, photonics, sensors, etc. Being a digital processing technology, materials are utilized only in the programed areas, hence reducing the consumption. This yields not only a major reduction of the materials impact in the environment, but also enables the use of materials that otherwise would be to expensive to use. Furthermore, sequential deposition of different materials is a natural processing step, reducing the factory capital and overhead costs.

Session 3: Immediate Challenges of Materials and Manufacturing

“Challenges and Key Priorities for the Automotive Semiconductor Value Chain,” Joyce Witowski, Sr. Director, Sustainable Manufacturing at NXP

The semiconductor industry is expected to grow to a $1T industry by 2030, driven by the rise of the “secure edge” through smart connected devices, factories, homes and, especially, cars. For the automotive industry, the chip manufacturing capacity crunch is likely to persist with the majority of semi equipment CAPEX investment in the leading edge technology nodes, whereas the bulk of the automotive chip demand is driven by the mature edge. Further investments are needed in the mature edge for Front End manufacturing and its supporting ecosystems (equipment, materials) to support the automotive chip demand.

There are three major societal pressures necessitating further investments in the Front End manufacturing ecosystem: 1) quality, driven by the stringent automotive requirements due to the complexity of collaborative systems and the high impact of potential failures – a “zero defect” quality mindset is required across the entire value chain; 2) supply chain resiliency: not only governmental restrictions, end customers are increasingly understanding the complexity of semiconductor supply chains. End customers will condition design awards for new chip devices on semi companies having a resilient semi supply chain. This means that “geo-diversity” is a key consideration for business continuity planning within the entire value chain; and 3) increased focus on sustainability necessitates a transition towards sustainable manufacturing. Increasingly, society will set expectations on carbon emission reduction programs to enable a more sustainable future. Each company within the semi value chain will need to recognize, calculate, set aggressive targets and report on their scope 1/2/3 emissions. End customers will condition design awards for new chip devices on semi companies having an aggressive and realistic carbon emission reduction roadmap, covering scope 1/2/3 emissions.

“Semiconductor PFAS Consortium Results and Opportunities,” Tim Yeakley, EHS Policy Manager at Texas Instruments, and Laurie Beu, Principal Consultant at Beu Consulting

Given the increasing interest and concern with perfluorinated chemicals that don’t readily degrade under normal environmental conditions, it is necessary to understand semiconductor uses and their supply chains uses so that industry and government actions will be adequately informed. This presentation will describe the basis of the concerns and how information was collected by some semiconductor sector suppliers and device manufacturers. A summary of the findings and some R&D opportunities will also be discussed.

“Unmasking the Challenges of Diborane Manufacturing and Supply,” Jeffrey Yoder, Senior Director HVM Product Management at Air Liquide

While not new, the use of diborane in semiconductor applications is evolving substantially. It was a niche product, used primarily for doping in CVD/Epi applications, and more recently as a reactant/seed for W metallization, which was a key enabler of 3D NAND structures. More recently, the increasing aspect ratio of these structures, as well as the emergence of new applications including some related to hard masks, have led to the need for finer control of the product and significantly increased volumes respectively.

While diborane is becoming an increasingly critical molecule for several manufacturing processes, it is challenging to manufacture and handle. For example, diborane is a thermally unstable and hazardous molecule and thus supplied in blends to minimize problems with its decomposition into heavier boranes. Second, while H2 is the best balance gas to stabilize it, some processes require blends in an inert gas (N2 or Ar). Thus, every diborane blend is a different product. Third, the demand for tighter product control combined with its unique properties has led to the implementation of very specific manufacturing processes and QC technologies. In this talk we will review those different aspects of manufacturing and delivering diborane reliably.

Session 4: Challenges of Equipment & Component Materials

“Solid Source Vaporization and Processes Enabled,” Bryan Hendrix, PhD, Fellow at Entegris

Solid precursors are required for many leading edge and emerging film deposition processes for semiconductor manufacture. The case is made for using these precursors. The technology to use these precursors in high volume manufacturing is demonstrated and described.

“ALD Protective Coatings for Critical Process Equipment Components,” Lassi Leppilahti, Application Manager at Beneq

Semiconductor device manufacturing processes often involve highly energetic, reactive plasma and other corrosive chemicals that cause damage to the equipment materials. This equipment wear can be a cause of process instability and a source of defects, such as particles. In practice it means lower yield and shorter maintenance intervals. Protective coatings are used to manage the problematic equipment wear.

Usually, protective coatings are made by anodization or thermal spray techniques. These current coatings have significant limitations such as line‑of‑sight requirement, poor thickness control, and film cracking and porosity. Furthermore, their purity and composition are limited by the properties of the raw materials. Because of the continuing trend of stricter stability requirements and lower defect tolerances the current coatings will soon become insufficient in the leading-edge device manufacturing.

Atomic layer deposited (ALD) films are conformal enabling the coating of complex three-dimensional structures such as the internal surfaces of showerheads, nozzles, and gas lines with high uniformity. The high purity and near zero defect density of ALD film are optimal for best performing protective coatings. There are no weak points for corrosive attack in the film and there are minimal critical impurities or particles released from the film during usage. Various film materials can be deposited on equipment parts using ALD. The commonly used materials alumina and yttria can be applied but also mixtures of these and many other elements are available in ALD processing.

Beneq is the manufacturer of the largest scale batch ALD equipment in the market. The P800 system is a highly versatile tool for coating a variety of equipment parts. In a single batch it can be used to coat various configurations of substrates such as a mismatching set of process kit parts, a high number of matching parts, or a set of gas lines.

“Hydrogen Recovery,” Zach Dunbar, PhD, Technology Manager at Edwards Vacuum

The semiconductor industry faces numerous sustainability challenges. These include waste and the circular economy, water use, air pollution, global climate change, and energy use. These topics are interdependent. Many processes use process gases that have significant embodied energy. Recovery and recycling of these gases not only reduces operating costs and improves supply chain resilience but also reduces the total carbon footprint of the process. To this end, Edwards is developing a hydrogen recovery system (HRS) capable of recovering EUV process waste hydrogen gas.  The HRS purifies and pressurizes the waste hydrogen to meet purity & pressure requirements and recycles the gas directly into the EUV lithography tool.  In partnership with IMEC, Edwards has demonstrated successful recycling into an active EUV tool from a leading EUV OEM.  Over 9 million standard liters (approximately 850 kg) of hydrogen have recycled with no negative impact to the EUV, while reducing EUV-related hydrogen consumption approximately 70%.  Performance data such as recovery rates, purity, energy consumption, as well as opportunities for further development will be discussed.

“Integrated Data Collaboration for Value Chain Ecosystem,” Chris Han-Adebekun, PhD, VP of Business Development at Athinia

Last three years, the semiconductor industry experienced its phenomenal growth driven by work-from- home economy while overcoming unprecedented global interruptions of logistics in supply chains. We are humbly taught that always “expect the unexpected” but “Failure is not an option”. Today, as semiconductor industry prepares to become 1 trillion in revenue and 1 trillion transistors per package, many prominent leaders have raised the strong need to collaborate among value chain players. To achieve 2X growth within a decade, amongst broad economic and political uncertainties, we believe that integrated data sharing mechanism and data driven innovations are critical to reach our collective goals.

In this presentation, we would like to demonstrate how data collaboration approach can be used to help improving ecosystem resilience among the value chain players. By joining a common data platform with the mutual confidence in data and IP security, participants can conduct simulations of reality, optimize operational plans, monitor KPIs with real-time dashboards, and execute proactive risk mitigation actions. Some of the practical industry use case studies and scenario analysis will be discussed for operation improvement and supply chain transparency.  Ecosystem-wide collaboration is no longer an option, but a must.

Session 5: Emerging Materials in R&D and Pilot Fabrication

“Materials at the Heart of Semiconductor Innovation,” Dr. Carolyn Duran, Vice President, Components Research at Intel Corporation

The role that materials play in driving semiconductor innovations over the decades cannot be overestimated.  Leaps in transistor, interconnect and packaging capabilities have been realized with matched leaps in materials and process innovations.  Dr. Duran will start by highlighting some of the key transitions, and the materials behind them, that have kept our industry on pace with Moore’s Law. However, as we look forward, the challenges are even greater as we try to solve for exponential growth in compute and data while simultaneously addressing key challenges around energy efficiency and sustainability.  With this lens, she will share key materials research areas that drive our next generations of innovations in this vibrant field.

“Dry Resist Materials, Equipment, and Process for Improving EUVL Capability and Extending Its Use Well Below the 1nm Node,” Benjamin Eynon, Senior Director, Advanced Technology Division at LAM Research

Extreme ultraviolet (EUV) lithography has been introduced into semiconductor IC high volume manufacturing (HVM) beginning at the 7nm node logic, and is being qualified at for an increasing proportion of litho steps at 5/3nm Logic and 16/14nm DRAM. A persistent challenge for the EUV scanner is to supply to the photoresist (PR) a high contrast image with enough photons to meet HVM productivity targets with acceptable dimensional and defectivity control.  Local stochastic variability in dimension and placement dominates the total dimension control budget, and reducing that variability by increasing the exposure dose comes at the cost of scanner throughput.

EUV scanner power and reliability have each made significant improvements toward performing at the HVM level over the last 10 years; however, photoresists have not kept pace with the increasingly stringent technology requirements. Today spin-on photoresists are unable to meet the sensitivity, resolution, edge roughness, and defectivity targets for the high volume manufacturing (HVM) of the most advanced technology nodes. This gap in photoresist readiness has driven customers to make compromises in design and cost and put significant pressure on downstream processes to correct for shortcomings in the lithography pattern, providing a significant opportunity for breakthrough innovation.

We discuss here our revolutionary technique to both apply EUV photoresist and develop latent images in the photoresist using dry technologies instead of the existing wet spin coating and development that have been in use over the last several decades. We will review the key mechanisms and advantages of dry resist processing over wet resist processing, and will report the latest results across a variety of key indices. This nascent technology has demonstrated best-in-class resist performance at leading edge design rules and now opens the door to a new level of performance in EUV lithography patterning.

“New Developments in Underlayers and Their Role in Advancing EUV Lithography,” Joyce Lowes, Dir. of Emerging Materials Technology at Brewer Science

Extreme ultraviolet (EUV) lithography is used to pattern the smallest features in advanced semiconductor devices. The demand for smaller devices with more capabilities requires industry innovation in EUV processes and materials. Additionally, EUV plays a critical role in the evolution of technology and enables the continuous advancement of the semiconductor roadmap, as it provides the capabilities of higher processing power while using less energy and providing higher performance. However, one of the biggest challenges facing EUV lithography is material requirements, recognizing the critical role underlayers play in the patterning of EUV lithography.

Unlike bottom antireflective coatings (BARCs), reflectivity control is no longer the driving mechanism for underlayers. Now, underlayers are necessary to support resist performance and to enable scaling of the process. In this paper, a variety of material approaches are introduced that offer process and defectivity improvements for traditional EUV lithography schemes. These materials demonstrate improved process window, depth of focus, and LWR/CDU, which can be achieved across a variety of EUV patterning applications.

“Photomask Materials – Challenges and Future Requirements,” Glen Scheid, Sr. Manager, Operations, Mask Technology Center at Micron

Photomasks are a critical component in the IC semiconductor supply chain. With the ramp of extreme ultraviolet (EUV) lithography the photomask supply chain is challenged in the areas of cost, lead-times, and capabilities. This talk will review materials challenges as viewed through the lens of a leading-edge photomask manufacturer. Key areas of the photomask supply chain including mask blanks, resists and pellicles will be covered along with discussion on where improvements are needed.

“Materials for Quantum,” Satyavolu Papa Rao, VP, Research at NY CREATES

This talk will begin with a rapid review of the applications of quantum information in areas ranging from computing and sensing to probing fundamental physics concepts. Following an overview of the various qubit modalities being pursued across the world, and a discussion on their relative strengths, the stage is set to explore how materials, their interfaces, and fabrication technologies will play a crucial role in enabling the scaling of quantum devices to tackle problems of importance to the world we live in.

“Model-Based Optimization of the Application Performance in Late-Stage Material Development,” Steven Eulig, Head of Business Development, Operations Digital Solutions at EMD Electronics

Materials suppliers are constantly researching new materials for application in the latest tech nodes. The goal of the late R&D – early scale-up stage is to maximize the application performance of the material while minimizing the expected cost of production and to ensure safe scale-up of the developed process. We discuss data-based approaches to accelerate this stage of material development.

“Materials & Technology Roadmap – Where have we been? And where are we going?,” Karey Holland, Ph.D., Chief Strategist at TECHCET

The leading edge semiconductor device technologies of Logic, DRAM and 3D NAND have distinct and challenging technology challenges as they progress from current device nodes to devices 5 or more years in the future.

3D NAND continues to evolved from current 276 layers (2xxL) to 512 layers (5xxL) and beyond. Lithography dimensions are expected to maintain sizes similar throughout the roadmap, but high aspect ratio etch, high aspect ratio ADL/CVD fill may increase. Materials used are also expected to transition – example is wordline electrodes.

DRAM will continue to scale from the 1β to 1Ϫ to 0α and beyond. As DRAM scales, dimensions continue to shrink and the capacitors are increasing in the z dimension and changing materials used. Future DRAM may transition to the “capacitorless” technology.

Advanced Logic is aggressively scaling. Current FinFET is in transition to the Gate-All-Around (GAA, also called nanosheets or nanoribbons) transistors. With this transition, significant changes are expected to occur including contact metallization, selective isotropic etches, and challenging ALD depositions, and wet chemical etches. In the second generation of GAA, power delivery is planned to move to backside power rails, adding more significantly different process steps. After GAA, development is working on CFET and later 2D materials for the transistors.